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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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rev.1.0, sep.19.2003, page 1 of 17 m61558fp power driver ic for 30-w 1-channel digital amplifiers rej03f0060-0100z rev.1.0 sep.19.2003 description the m61558fp is a power driver ic for digital power amplifiers. the ic incorporates both pre-drivers and the output- stage n-channel power mos fet, for a single chip implementation of a 30-w single-channel digital amplifier for audio applications. features ? on-chip n-channel power mos fet ? fast pwm switching operation ? on-chip diode for boot strap ? various on-chip protective circuits ? vdd under detection circuit ? over-temperature protection circuit ? over-current protection circuit recommended operating conditions power-supply voltage for pre-drive stage: vdd = 12 v (pre-driver stage power-supply voltage) output-stage power-supply voltage: vd = 21 v (typ.) < 16 v (min.) to 24 v (max.), rl = 4 (min.), 6 (typ.), 8 (max.) ?
m61558fp rev.1.0, sep.19.2003, page 2 of 17 system block diagram pwm processor mcu m61558fp level shifter level shifter inb+ out a ina+ vda hba vsa out b vdb hbb vsb over-temperature protection detector over current protection ch1 ch2
m61558fp rev.1.0, sep.19.2003, page 3 of 17 sample application circuit and pin assignments vd=21 (16 to 24)v (max. current: about 7.5 a) 470 f 10 ? rl=4 to 8 1000pf (for emi) damping circuit m61558fp 1 2 3 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 30 29 28 27 26 25 24 23 vdd = 12 v (from 10.8v to 13.2v) prout gnd 0.022uf 1u 1u vz=33v 22 vdb vdb outb outb vsb vsb lsginb hsginb hbb vddb hsgout lsgoutb inb + en fila5v gndb 4 vda vda outa outa vsa vsa lsgina hsgina hba vdda hsgout lsgouta vddp ina + gnda prout 31 filb5v gndp dtcntl sub(g n d prvd filp5v 10 6.2k 10uh 10uh inb + ina + sub(g nd sub(g nd sub(g nd en prlpfvd 10nf 10 pwm processor mcu 100 f 0.1 f 10 f 10 f 2.7 0.1 lpf 10 f 10 f 10 f 2.7 10 47 f lpf 47 f 0.022 f 0.1 f vz=33v 0.1 0.1 0.1
m61558fp rev.1.0, sep.19.2003, page 4 of 17 block diagram prlpfvd outb vddb gndb vsa prout outa vdb vda gndp vddp en ina gnd a vsb pr vd 28 5 18 3 22 15 25 30 20 19 4 6 41 38 39 37 40 42 12 2 1 21 34 35 29 11 lsginb hsgin b hsgout b lsgoutb hbb hsgin lsgin hsgout hba 7 lsgout 9 13 31 33 vdd a 17 fila5 dead-time control dead-time control level shifter level shifter 16 filb5 v 27 inb 26 dtcnt 24 filp5 23 8 dead-time control circuit protector control logic vdd under voltage detector over-temperatire protection circuit over-current protection circuit
m61558fp rev.1.0, sep.19.2003, page 5 of 17 pin descriptions pin no. pin name pin description 1, 2 vsa ground pin for the a-side power-output stage 3, 4 outa a-side power-output pin 5, 6 vda power-supply pin for a-side power-output stage 7 lsgina mos fet input pin for a-side (l) a-side power module 8 hsgina mos fet input pin for a side (h) 9 hsgouta a side (h) pre-buffer output 10 nc connected to ground 11 hba a pin for a side (h) boot strap.* 12 vdda a-side pre-driver power-supply pin 13 lsgouta a-side (l) pre-buffer output 14 nc connected to ground 15 gnda a-side pre-driver ground pin 16 fila5v filter pin for a-side 5-v internal generation power-supply a-side pre- control module 17 ina+ a-side pwm + input pin (cmos input) 18 prvd power-supply pin for over current protection. connected to vd power supply. 19 prlpfvd filter pin for over-current protection circuit 20 vddp power-supply pin for protection circuit block 21 prout protection detector output pin. when protection condition is detected, low level (if pin is pulled up) is output (open drain output). 22 gndp ground pin for protection circuit block 23 filp5v filter pin for generation of 5-v internal power-supply for protection circuits 24 dtcntl for connection to a resistor for dead-time control a, b common protec- tion module 25 en enable pin that release from the protection state 26 inb+ b-side pwm + input pin (cmos input) 27 filb5v b-side 5-v internal generation power-supply filter pin 28 gndb b-side pre-driver ground pin 29 lsgoutb b-side (l) pre-buffer output 30 vddb b pre-driver power-supply pin 31 hbb apm for b-side (h) boot-strap capacitor circuit. 32 nc connected to ground b-side pre- control module 33 hsgoutb b side (h) pre-buffer output 34 hsginb b side (h) mos fet input pin 35 lsginb b side (l) mos fet input pin 36 nc connected to ground 37, 38 vdb b-side power-output stage power-supply pin 39, 40 outb b-side power-output pin b-side power module 41, 42 vsb b-side power-output stage ground pin note: * adjacent power-module pins that have the same names must be connected with the shortest possible wiring lengths.
m61558fp rev.1.0, sep.19.2003, page 6 of 17 absolute maximum ratings parameter symbol ratings unit conditions hba, hbb max. operating voltage hba, hbb 39 v hba, hbb pin voltage (operational setting) vda, vdb max. operating voltage vda, vdb 25 v vda, vdb pin voltage (operational setting) absolute max. voltage rating vdd 15 v vdd power-supply voltage voltage applied to input pins vin ? 0.3 to 5.5 v allowable dissipation pd 3.6 w ta = 25 c (when mounted on the board specified by renesas; see note 1) thermal derating k 28.8 mw/ c when mounted on the board specified by renesas; see note 1) junction temperature tj 150 c operating temperature ta ? 20 to +60 c storage temperature tstg ? 40 to +125 c notes: 1. the specifications of the board specified by renesas are given below for reference. 2. maximum allowable power dissipation pd = 11.4 w (ambient temperature ta = 25 c) with an ideal heat sink. thermal derating curve 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 25 50 75 100 125 150 ambient temperature ta (?c) *1 *2 infinite heat sink power dissipation pd (w)
m61558fp rev.1.0, sep.19.2003, page 7 of 17 layer 1 (surface) layer 2 (rear) *1 thermal derating characteristics measured for the board specified by renesas (board specifications) material: glass epoxy fr-4 dimensions: 70 70 mm thickness: t = 1.6 mm (wiring specifications for layers 1 and 2) material: copper thickness: t = 18 mm precautions on usage 1. this product radiates heat even during normal operation, and reaches high temperatures. there is a possibility that characteristics failure or breakdown, including in peripheral components and circuits, may cause this product or peripherals to reach abnormally high temperatures. also, please take special care when using this product as the final stage, since it may then be susceptible to damage because of external factors. this product is designed for consumer applications. accordingly, please use it within the specified thermal conditions. usage of the product in more relaxed thermal conditions may lead to malfunctions or damage to the product. 2. this product incorporates an over-current protection circuit which terminates the pwm operation when the peak instantaneous current from the vda or the vdb power supply exceeds 7.5 a (designed value). please note that it is never required to supply more current than this. the maximum-current value is roughly below 3 a during operation with a standard 4- ? load. in usage, care is required with regard to the stability of the power-supply voltage. 3. detection of an abnormality (when the prout pin (pin 21) becomes low) indicates a possibility of over current, so eliminate the cause, such as shorting of the output pins, and release the ic from the protection state (input low level on the en pin (pin 25)). 4. this product includes mos fet and cmos logic circuits. accordingly, electrostatic break down or latch-up may be generated within these elements. please take the same care in using this product as in any case where mos fet and cmos logic lsis are in use.
m61558fp rev.1.0, sep.19.2003, page 8 of 17 recommended operating condition limits item symbol min. typ. max. unit condition vd power-supply voltage vd 16 21 24 v vda (pins 5, 6), vdb (pins 37, 38) vdd power-supply voltage vdd 10.8 12.0 13.2 v vdda (pin 12), vddb (pin 30), vddp (pin 20) pwm frequency fpwm 0.7 1.5 mhz ina+ (pin 17), inb+ (pin 26) min. operating pulse width tpw min 40 ? ? ns ina+ (pin 17), inb+ (pin 26) high input voltage vinh 4.0 ? 5.0 v ina+ (pin 17), inb+ (pin 26) low input voltage vinl 0.0 ? 0.8 v ina+ (pin 17), inb+ (pin 26), en (pin 25) notes: 1. pwm operation do not input a signal shorter than the minimum pulse width, since this may lead to unstable operation or, in the worst case, damage to the product. since boot-strap operation is performed, an input signal with aperiodical high and low levels may lead to abnormal operation. ensure that the pwm signal has periodical high and low levels. the capacitance of the capacitor for boot-strapping in the sample application diagram is for the product in operation at 768 khz. the thermal conditions, etc., become looser with operation at lower pwm frequencies. 2. power-supply voltage the normal operating condition for this product is vdd voltage < vd voltage, so ensure that this is the state during normal operation. setting a lower vdd voltage increases the margin against damage but carries the danger of the under voltage detection circuit malfunctioning, so please ensure that vdd is maintained at 9 v or more. 3. mounting (board) the board layout must be capable of handling the same high frequencies and high levels of power as are handled by this ic. furthermore, components must be selected in consideration of both audio-frequency and high-frequency characteristics. please external note that large surges are generated by parasitic inductances during high-speed switching. this ic is designed specifically for bridge-tied load (btl) operation, so the design focus was on symmetry of sides a and b. the pattern on the board must also be highly symmetrical for btl configuration.
m61558fp rev.1.0, sep.19.2003, page 9 of 17 electrical characteristics (unless otherwise noted, ta = 25 c, vddp, vdda, b = 12 v, vda, b = 21 v) limits item symbol min. typ. max. unit condition of measurement current drawn by the circuit vdd current circuit (suspended) iddqs ? 15 ? ma pwm-suspended state vdd current circuit iddq ? 35 ? ma no signal (f = 768 khz, duty cycle = 50%) vd current circuit ? 40 ? ma no signal (f = 768 khz, duty cycle = 50%) signal interfaces high input signal vih 2.3 ? ? v pins ina+, inb+, en low input signal vil ? ? 1.0 v pins ina+, inb+, en high level input current iih ? 10 10 a pin en low level input current iil ? 260 ? 130 ? 65 a pin en low output voltage vol ? 0.4 v pin prout: iol = 1 ma high-output (leakage) current ioh ? 10 a pin prout: voh = 5 v protection detectors vdd under voltage detection level vddr 5.0 7.0 9.0 v between vdd and gnd, drop- detected to normal hysteresis in vdd-detection voltage vddh ? 0.5 ? v normal to under voltage over temperature protection start temperature tsd+ 150 c normal to over-temperature protection state* over temperature protection end temperature tsd ? 130 c over-temperature to normal state* diode characteristics for boot-strap diode forward-direction voltage vfl ? 0.75 ? v hb output current = 100 a diode forward-direction voltage vfh ? 1.0 ? v hb output current = 100 ma diode dynamic resistance rdon ? 0.7 ? ? hb output current = 100 ma gate driver for low-side power transistor: ?on? voltage low level output voltage vol ? 0.5 ? v ilo = 100 ma high level output voltage voh ? ? 0.75 ? v iho = ? 100 ma ? ? gate driver for high-side power transistor: ?on? voltage low level output voltage vol ? 0.5 ? v ilo = 100 ma high level output voltage voh ? ? 0.75 ? v iho = ? 100 ma ? ? *: note that tsd+, tsd ? are designed values for the ic?s internal temperature.
m61558fp rev.1.0, sep.19.2003, page 10 of 17 (unless otherwise noted, ta = 25 c, vddp and vdda/b = 12 v, vda/b = 21 v) limits item symbol min. typ. max. unit condition of measurement output-stage dmos transistor on resistance breakdown voltage between drain and source bvds 35 ? ? v ileak=1ma on resistance between drain and source rds(on) ? 0.20 ? ? id=100ma input/output timing reference input operating frequency 1/tpf ? 768 ? khz boot-strap c = 0.022 uf min. input pulse width tpw 40 ? ? ns period = 1.3 us (f = 768 khz) dead-time setting pin 24 output voltage vdtc ? 1.35 ? v connected resistance: 6.2 k ? (data for reference) ac characteristics note: the reference values when the evaluation board specified by renesas is used. (unless otherwise specified, ta = 25 c, vddp and vdda/b = 12 v, vda/b = 21 v) rated value item symbol min. typ. max. unit reference board setting condition measurement condition output power 1 po1 ? 30 ? w sine, 1 khz/0 db, modulation depth = 90% thd+n=1%,rl=6 ? , vda/b=24v lpf=20khz, hpf=400hz output power 2 po2 ? 30 ? w sine, 1 khz/0 db, modulation depth = 90% thd+n=1%,rl=4 ? , vda/b=21v lpf=20khz, hpf=400hz total harmonic distortion thd+n ? 0.04 ? % sine, 1 khz/0 db, modulation depth = 50% rl=4 ? , lpf=20khz, hpf=400hz noise voltage vno ? 150 ? vrms the mute signal is inputed a-weighted filter/ lpf=20khz power efficiency eff ? 85 ? % sine, 1 khz/0 db, modulation depth = 90% po=30w, rl=4 ? note: in the heat-radiation state of attachment to the board specified by renesas, the m61558fp can continuously output 10 w (refer to the thermal derating curve on page 5). when more than 10 w is continuously output, heat- radiation design measures such as heat sinks are required. description of additional functions dead-time control the dead-time value given below sets a period between lsgouta(b) and hsgouta(b) at the gate-driver outputs. this prevents through-current-induced damage to the output-stage power transistor. the dead-time setting is adjusted by the value of the external resistor on dtcntl (pin 24).
m61558fp rev.1.0, sep.19.2003, page 11 of 17 note : the given values are design values, and the actual dead time is affected by the operating conditions (gate- resistor value, switching characteristics, etc.) of the power transistor. ina(b) hsgout a(b) lsgout a(b) dead time dead time timing of input and output operations input pulse width (high level) 10 20 30 40 20 15 10 5 0 50 dead time and resistance setting (reference values for the pre-driver module) dead time dt (ns) set resistance rdt (k ? )
m61558fp rev.1.0, sep.19.2003, page 12 of 17 internal protective circuits 1. vdd under voltage detection circuit when the vdd power-supply voltage falls by a certain amount, the vdd under voltage protective circuit operates to prevent malfunctions of the ic. when an abnormality is detected, the output transistor on the h side is switched off, the output transistor on the l side is switched on, and a low level is output from the output pin. for the sake of automatic resumption, a low level is not output from prout (pin 21). of the protection states, this is only the case for abnormal voltage-drop detection. the vdd detection circuit is connected to the common vdd power-supply pin, vddp (pin 20). please set up ic-external wiring to connect the vdda/b (pins 12, 30) to vddp. 2. over temperature protection circuit the ic incorporates an over temperature protection circuit (thermal shutdown circuit) that protects the ic from thermal damage when the temperature of the ic (chip) rises because of an abnormality. the protection circuit is activated before the ic?s internal junctions, etc., reach the thermal-damage temperature, and remains so until the temperature falls to the hysteresis condition, regardless of the state of the en pin (pin 25). in the excessive- temperature condition, all output transistors are turned off, the output pins are released (open), and a low level is output from prout to issue a notification about the abnormal state. 3. over current protection circuit this ic incorporates an excessive current protection circuit which terminates the pwm operation when the peak instantaneous value of current supplied from the vda or vdb power supply exceeds 7.5 a (designed value). in the protection mode, all output transistors are switched off, all output pins are released (open), and a low level is output from prout to notify the system of the abnormal state. note: the abnormality is detected on the positive side of the power-stage power supply. the conditions for detecting a load short between output pin and vdd. vdd are not more strict short between both output pins or between output pin and ground. note that when shorting between vdd occurs, detection is not possible until the abnormality affects the positive side of the power supply, so the protective operation may not be performed. functions when an abnormality is detected when an abnormality is detected, the ic operates asynchronously with respect to the pwm inputs (ina+, inb+), controls the output-stage n-channel transistor (h or l side) and enters the protection state. the states of the prout and out outputs and the states of each output-stage transistor are given in the table below. after the low level has been placed on prout, the protection state is maintained until the en signal is low. state of output stage during protection operation outa output- stage transistor outb output- stage transistor protection prout output in case of abnormality outa output pin outb output pin h side l side h side l side vdd voltage-drop protection no change (high) low low off on off on over temperature, over-current protection output low, held until low level is placed on en open open off off off off resuming from abnormality detection resumption to signal output from the individual abnormal state varies with the corresponding protective circuit. after the conditions for resumption have been satisfied, resumption occurs on the rising edge of either ina+ or inb+, whichever is earlier. the conditions for resumption from each abnormal state are given in the table below.
m61558fp rev.1.0, sep.19.2003, page 13 of 17 conditions required for resumption from abnormal states abnormal state condition for resumption vdd under voltage after the voltage has returned to the normal level and this has been confirmed by the internal vdd detection circuit, the ic resumes normal operation on the next rising edge of either ina+ or inb+. over temperature, over current after the state has returned to normal, the condition for resumption is the falling edge of en. the ic then returns to normal operation on the next rising edge of either ina+ or inb+. timing chart for protector detection-output prout (pin 21) and enable input en (pin 25) detctiond protect detected (over temperature or over current) 1 to 10 s or less on input of the low level to en (pin 19), normal operation resumes on the next rising edge of input signal ina+ or inb+. protect operation (end of protect evnaition) ina+ or inb+ power-output stage fet control normal operation normal operation recovery of prout (on the falling edge of en) protector detection-circuit output prout (pin 21) enable input en (pin 25)
m61558fp rev.1.0, sep.19.2003, page 14 of 17 lpf circuit the output lpf circuit must have characteristics in accord with the signal-frequency band and characteristic impedance value of the speaker that constitutes the load. the simplest example is a second-order butterworth filter in an lc configuration. damping circuit when the speaker is removed, the frequency characteristics of the low-pass filter may lead to problems of high-band characteristics such as peaking. accordingly, a high-band damping circuit should be installed in parallel with the speaker. (take the allowable power, etc., of the damping resistor into consideration.) zener diode for surge protection ringing, etc., occurs during the high-speed switching operation of this ic. during short-circuit, connection to ground or vdd of load, very large surge voltages are generated. when the surge voltage exceeds the voltage tolerance of the transistors (step-down voltage between source and drain, etc.), the ic may be damaged. we recommend that you prevent damage to this ic by connecting a zener diode for surge protection to the output pins (select a zener voltage slightly below 35 v). precautions on wiring for the protective circuits prvd (pin 18) is wired to the protective detection circuits. use as short a wiring run as is possible to connect this pin to a point on the vd power-supply line near the vd pin. this point should not be readily affected by variation in voltages due to power supply and the operating conditions. please take care because this may affect the characteristics of the protective circuits or damage the ic. measures against emi please note the need to reduce the levels of unwanted radiation components produced by high-speed switching operation. for example, apply countermeasures such as raising the order of the output lpf circuit, or attaching a capacitor with a value of about 1000 pf to the speaker pin. single-ended operation this ic is for bridge-tied load (btl) operation, but single-ended operation for an independent half-bridge configuration is possible. in this case, note that performance changes (e.g. 30 w x 1 ch. becomes 7.5 w x 2 ch). also, other parts of the ic are designed on the specific assumption of btl operation, so sufficient evaluation and examination is required. pop noise when turning the power supply on and off one simple countermeasure against pop noise is to ensure that vd (power-stage power-supply voltage ) is only turned on and off while vdd (power-supply voltage of the pre-driver stage) is applied. if this measure is ignored, pop noise may occur when the power supply is turned on or off. we also recommend operation under the condition vdd < vd. consider turning the power supply on and off in the following sequence.
m61558fp rev.1.0, sep.19.2003, page 15 of 17 v t vd power-supply voltage (power-stage) v d p o w e r - s u p p l y v o l t a g e ( p o w e r - s t a g e ) vdd power-supply voltage v d d p o w e r - s u p p l y v o l t a g e (pre-driver stage) ( p r e - d r i v e r s t a g e ) actual usage range a c t u a l u s a g e r a n g e heat sink unlike the molded resin surface, the metal side of the package for heat radiation is slightly concave.take this structure into consideration when designing a heat sink for use with high output levels. capacitor for boot-strapping this ic is designed for pwm operation at around 768 khz (high-speed pwm operation in the hundreds of khz order). accordingly, the value of the capacitor for boot-strapping in the diagram of the example application circuit is for such operation. if a large change is to be made to the pwm frequency, a correspondingly change in the value of this capacitor is required. note that such usage was not presupposed in the design of this ic.
m61558fp rev.1.0, sep.19.2003, page 16 of 17 muting operation by force the output is forcibly muted by using a resistor to pull the prlpfvd pin (pin 19) down to ground (signal output is terminated and the output terminals enter the hi-z open state; refer to the figure below). to cancel muting, release pin 19 from the pulled-down state, and then input a cancellation pulse on the en pin (pin 25) in the same way as is used to cancel the protection state. please note the following points: ? muted operation is only possible during normal operation; that is, it is not possible in transient states, such as while turning the power supply on or off. ? for actual usage, please thoroughly evaluate and examine the forcible mute operation. note: the above setting assures operation by ensuring the flow of a strong current. decreasing the resistance below this level has no effect. m61558fp mute circuit r = 4.2 k ? (see note) 19
m61558fp rev.1.0, sep.19.2003, page 17 of 17 package dimensions 42p9r-e note : please contact renesas technology corporation for further details.
? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas tech nology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices

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